FETCH DECODE EXECUTE CYCLE

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 FDEC (FETCH DECODE AND EXECUTE CYCLE) shows how basically a computer CPU works.

First understand the components of CPU =>

1.    ALU (Arithmetic Logic Unit) - From its name, we come to know that it it performs arithmetic operation of CPU like addition and subtraction.

2.    PC (Program Counter) - Address where computer will look for instruction

3.    MAR (Memory Address Register) - Computer needs somewhere to store address of current instruction being executed.

4.    MDR (Memory Data Register) - Data copied from address present in MAR is stored in MDR.

5.    IR (Instruction Register) - If data in MDR is instruction then it is stored in IR .

6.    Control Unit - data from IR is fetched and decoded into two parts opcode and operand by Control Unit

7.    Acc (Accumulator) - Executed data is stored in MDR if it is not instruction then it is stored in Accumulator.

FETCH:

1.    Computer will look for instruction that is present in address which is the value present in PC.

2.    Computer stores the addresses taken from PC in MAR.

3.    Control unit sends MEMORY READ SIGNAL to read the data from address present in MAR then takes it and stores it in MDR through the data bus.

4.    Data fetched from MAR address is instruction it is stored in IR.

5.    As the computer come to know that it is at the end of the fetch cycle it increments the PC.So that it can start its new fetch cycle asap after executing the step.

DECODE:

1.    Data in the instruction pointer is sent to the control unit through the data bus and it is split into two parts. The first        is OPERATOR and the second is OPERAND(address)

EXECUTE:

1.    Value is operand is address, So Computer goes to that address and fetches the value and passed to           MDR.

2.    As the value in MDR is not an instruction so it will pe copied into Accumulator.




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